1 HV232 v pp ?v nn 200v HV232pj HV232fg HV232x low charge injection 8-channel high voltage analog switch with bleed resistors ordering information features ? hvcmos technology for high performance ? very low quiescent power dissipation ?10 a ? output on-resistance typically 22 ohms ? integrated bleed resistors on the outputs ? low parasitic capacitances ? dc to 10mhz analog signal frequency ? -60db typical output off isolation at 5mhz ? cmos logic circuitry for low power ? excellent noise immunity ? on-chip shift register, latch and clear logic circuitry ? flexible high voltage supplies ? surface mount package available package options general description the supertex HV232 is a low charge injection 8-channel high- voltage analog switch integrated circuit (ic) with bleed resistors. the device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. the bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric trans- ducers. input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. to reduce any possible clock feed-through noise, latch enable bar (le) should be left high until all bits are clocked in. using hvcmos technology, this switch combines high voltage bilateral dmos switches and low power cmos logic to provide efficient control of high voltage analog signals. this ic is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +50v/?50v, or +100v/?00v. 28-lead plastic 48-lead tqfp die chip carrier absolute maximum ratings* v dd logic power supply voltage -0.5v to +15v v pp - v nn supply voltage 220v v pp positive high voltage supply -0.5v to v nn +200v v nn negative high voltage supply +0.5v to -200v logic input voltages -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65 c to +150 c power dissipation 28-pin plcc 1.2w 48 lead tqfp 1.0w * absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. HV232 05/01/00 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for complete liability information covering this and other supertex products, refer to the supertex 1998 databook. preliminary
2 HV232 electrical characteristics dc characteristics (over recommended operating conditions unless otherwise noted) 30 26 38 48 i sig = 5ma v pp = 40v, 25 22 27 32 i sig = 200ma v nn = -160v small signal switch (on) r ons 25 22 27 30 ohms i sig = 5ma v pp = 100v, resistance 18 18 24 27 i sig = 200ma v nn = -100v 23 20 25 30 i sig = 5ma v pp = 160v, 22 16 25 27 i sig = 200ma v nn = -40v small signal switch (on) ? r ons 20 5.0 20 20 % i sw = 5ma, v pp = 100v, resistance matching v nn = -100v large signal switch (on) r onl 15 ohms v sig = v pp - 10v, i sig = 1a resistance output switch shunt r int 20 35 50 k ? output switch to r gnd resistance switch off leakage i sol 5.0 1.0 10 15 av sig = v pp - 10v per switch dc offset switch off 300 100 300 300 mv no load dc offset switch on 500 100 500 500 mv no load pos. hv supply current i ppq 10 50 a all sws off neg. hv supply current i nnq -10 -50 a all sws off pos. hv supply current i ppq 10 50 a all sws on, i sw = 5ma neg. hv supply current i nnq -10 -50 a all sws on, i sw = 5ma switch output 3.0 3.0 2.0 2.0 a v sig duty cycle 0.1% peak current output switch frequency f sw 50 khz duty cycle = 50% 6.5 7.0 8.0 v pp = 40v, v nn = -160v i pp supply current i pp 4.0 5.0 5.5 ma v pp = 100v, v nn = -100v 4.0 5.0 5.5 v pp = 160v, v nn = -40v 6.5 7.0 8.0 v pp = 40v, v nn = -160v i nn supply current i nn 4.0 5.0 5.5 ma v pp = 100v, v nn = -100v 4.0 5.0 5.5 v pp = 160v, v nn = -40v logic supply i dd 4.0 4.0 4.0 ma f clk = 5mhz, v dd = 5.0v average current logic supply i ddq 10 10 10 a quiescent current data out source current i sor 0.45 0.45 0.70 0.40 ma v out = v dd - 0.7v data out sink current i sink 0.45 0.45 0.70 0.40 ma v out = 0.7v logic input capacitance c in 10 10 10 pf 0 c +25 c +70 c characteristics sym units test conditions min max min typ max min max 50khz output switching frequency with no load
3 HV232 electrical characteristics ac characteristics (over operating conditions v dd = 5v, unless otherwise noted) 0 c +25 c +70 c characteristics sym min max min typ max min max units test conditions set up time before le rises t sd 150 150 150 ns time width of le t wle 150 150 150 ns clock delay time to data out t do 150 150 150 ns time width of cl t wcl 150 150 150 ns set up time data to clock t su 15 15 8.0 20 ns hold time data from clock t h 35 35 35 ns clock freq f clk 5.0 5.0 5.0 mhz 50% duty cycle f data = f clk /2 clock rise and fall times t r , t f 1.0 1.0 1.0 s turn on time t on 5.0 5.0 5.0 sv sig = v pp -10v, r l = 10k ? turn off time t off 5.0 5.0 5.0 sv sig = v pp -10v, r l = 10k ? 20 20 20 v pp = 160v, v nn = -40v maximum v sig slew rate dv/dt 20 20 20 v/ns v pp = 100v, v nn = -100v 20 20 20 v pp = 40v, v nn = -160v off isolation ko -30 -30 -33 -30 db f = 5mhz, 1k ? //15pf load -58 -58 -58 db f = 5mhz, 50 ? load switch crosstalk k cr -60 -60 -70 -60 db f = 5mhz, 50 ? load output switch isolation i id 300 300 300 ma 300ns pulse width, diode current 2.0% duty cycle off capacitance sw to gnd c sg(off) 5.0 17 5.0 12 17 5.0 17 pf 0v, 1mhz on capacitance sw to gnd c sg(on) 25 50 25 38 50 25 50 pf 0v, 1mhz
4 HV232 ac characteristics (over operating conditions v dd = 5v, unless otherwise noted) symbol parameter value v dd logic power supply voltage 1, 3 4.5v to 13.2v v pp positive high voltage supply 1, 3 40v to v nn + 200v v nn negative high voltage supply 1, 3 -40v to -160v v ih high-level input voltage v dd -1.5v to v dd v il low-level input voltage 0v to 1.5v v sig analog signal voltage peak to peak v nn +10v to v pp -10v 2 t a operating free air-temperature 0 c to 70 c notes: 1 power up/down sequence is arbitrary except gnd must be powered-up first and powered-down last. 2v sig must be v nn v sig v pp or floating during power up/down transistion. 3 rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. operating conditions * v pp = 40v, v nn = -160v, r l = 50 ? v pp = 100v, v nn = -100v, r l = 50 ? v pp = 160v, v nn = -40v, r l = 50 ? 150 150 150 150 150 150 mv output voltage spike +25 c units characteristics sym test conditions min typ max +v spk -v spk +v spk -v spk +v spk -v spk electrical characteristics
5 HV232 test circuits switch off leakage i sol v pp 5v v nn v pp v nn v dd gnd v pp e10v dc offset on/off v pp 5v v nn v pp v nn v dd gnd v out t on /t off test circuit v pp 5v v nn v pp v nn v dd gnd v pp e10v r l 10k ? v out isolation diode current i id v pp 5v v nn v pp v nn v dd gnd v nn v sig crosstalk k cr = 20log v out v in v in =10v pep @5mhz nc 50 ? v pp 5v v nn v pp v nn v dd gnd 50 ? charge injection v pp 5v v nn v pp v nn v dd gnd v sig v out 1000pf q = 1000pf x ? v out ? v out output voltage spike v pp 5v v nn v pp v nn v dd gnd v out 1k ? r l 50 ? +v spk ev spk off isolation k o = 20log v out v in v in =10v pep @5mhz v pp 5v v nn v pp v nn v dd gnd r l v out open r gnd r gnd open r gnd r gnd r gnd r gnd r gnd r gnd
6 HV232 data in le clock data out off on out (typ) v 50% 50% 50% 50% t wle t sd t su t h 50% 50% t off 50% t do t on t wcl clr d n 1 d n d n + 1 50% 50% 90% 10% logic timing waveforms block diagram d le cl le cl d le cl d le cl d le cl d le cl d le cl d le cl d le cl 8 bit shift register level shifters output switches latches sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 v pp v nn v dd rgnd d out d in clk
7 HV232 notes: 1. the eight switches operate independently. 2. serial data is clocked in on the l h transition clk. 3. the switches go to a state retaining their present condition at the rising edge of le. when le is low the shift register data flows through the latch. 4. d out is high when switch 7 is on. 5. shift register clocking has no effect on the switch states if le is h. 6. the clear input overrides all other inputs. d0 d1 d2 d3 d4 d5 d6 d7 le cl sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 llloff hllon llloff hllon llloff hllon llloff hllon lll off hll on lll off hll on lll off hll on lll off hll on x x x x x x x x h l hold previous state x x x x x x x x x h off off off off off off off off truth table
8 HV232 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 fax: (408) 222-4895 www.supertex.com 05/01/00 pin configurations package outlines HV232 28 pin j-lead pin function pin function 1 sw3 15 n/c 2 sw3 16 d in 3 sw2 17 clk 4sw2 18le 5sw1 19cl 6 sw1 20 d out 7 sw0 21 sw7 8 sw0 22 sw7 9 n/c 23 sw6 10 v pp 24 sw6 11 r gnd 25 sw5 12 v nn 26 sw5 13 gnd 27 sw4 14 v dd 28 sw4 4 26 25 19 top view 28-pin j-lead package 27 28 1 2 3 24 23 22 21 20 12 18 17 16 15 14 13 5 11 678910 HV232 48-pin tqfp pin function 1sw5 2 n/c 3sw4 4 n/c 5sw4 6 n/c 7 n/c 8sw3 9 n/c 10 sw3 11 n/c 12 sw2 13 n/c 14 sw2 15 n/c 16 sw1 17 n/c 18 sw1 19 n/c 20 sw0 21 n/c 22 sw0 23 n/c 24 v pp pin #1 pin 1 top view 48-pin tqfp pin 12 pin function 25 v nn 26 n/c 27 r gnd 28 gnd 29 v dd 30 n/c 31 n/c 32 n/c 33 d in 34 clk 35 le 36 clr 37 d out 38 n/c 39 sw7 40 n/c 41 sw7 42 n/c 43 sw6 44 n/c 45 sw6 46 n/c 47 sw5 48 n/c
|
